Fault Tolerance and Power Consumption Analysis on Chip-Multi Processors Architectures

With continuous scaling in CMOS technology thenumber of transistors grows more and more in a single die. Today Chip multiprocessors (CMPs) are the most architecturethat used in the computer industry to utilize the huge numbersof transistors. Reliability beside performance and powerdissipation is the most important metric in a processor. Onethe key challenge in employing these enormous transistors isthe unwanted effect of transient and permanent faults, whichthreat the reliability of a CMP. Recently, in order to increasereliability Redundant MultiThreading (RMT) approaches areproposed. In RMT methods, each execution thread duplicated, and these two copies of original thread run on different coreson CMP. Some of most important of execution results such asstore value and store address result will be compared and ifthere is no mismatch execution continue; otherwise the errorsignal will be active. In these work we implement RMT on agate level model of a two-way CMP and estimate failure rate inRMT processor by using of fault injection method and also wecalculate power dissipation and performance overhead of thistechnique. Our simulation experiments show that RMT has91.7% fault detection in respect to 4% power overhead. Performance degradation of RMT fault tolerance techniques isabout 29%. By comparing RMT with traditional informationredundancy techniques such as hamming code we found thatpower consumption in RMT fault tolerance techniques is 20-40 times higher than traditional ones.