DocumentCode
1726489
Title
On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs
Author
Liu, Y.X. ; Endo, K. ; O´uchi, S. ; Kamei, T. ; Tsukada, J. ; Yamauchi, H. ; Ishikawa, Y. ; Hayashida, T. ; Sakamoto, K. ; Matsukawa, T. ; Ogura, A. ; Masahara, M.
Author_Institution
Nanoelectron. Res. Inst., AIST, Tsukuba, Japan
fYear
2010
Firstpage
101
Lastpage
102
Abstract
The Vt variability in scaled FinFETs with gate length (Lg) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., work-function variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (TSi) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the Vt of multi-FinFETs with the same gate area reduces with increasing the number of fins.
Keywords
MOSFET; elemental semiconductors; etching; silicon; Si; fin thickness; gate length; gate oxide charge; gate oxide thickness; gate-stack origin; multiFinFET; scaled FinFET; threshold voltage variability; wet etching; work-function variation; FinFETs; Fluctuations; Logic gates; Materials; Tin; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location
Honolulu
Print_ISBN
978-1-4244-5451-8
Electronic_ISBN
978-1-4244-5450-1
Type
conf
DOI
10.1109/VLSIT.2010.5556187
Filename
5556187
Link To Document