Title :
Geometry effect on CMOS transistor stability under DC gate stress
Author :
Chin, David ; Pan, Sam ; Wu, Ken
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The authors show that transistor degradation is aggravated with an increase in channel length (L) and width (W) for negative gate bias stress, different from the W/L ratio dependence for positive stress reported previously. Nonuniform interface-state generation is believed to be the dominant degradation mechanism for negative stress, whereas negative trapped charge is the prevalent cause of instability for positive stress. This geometry effect needs to be considered when estimating CMOS transistor stability.<>
Keywords :
CMOS integrated circuits; circuit reliability; electron traps; hot carriers; insulated gate field effect transistors; interface electron states; semiconductor device testing; CMOS transistor stability; DC gate stress; channel length; channel width; geometry effect; negative gate bias stress; negative trapped charge; nonuniform interface state generation; transistor degradation; CMOS logic circuits; Circuit stability; Current measurement; Degradation; Digital integrated circuits; Geometry; MOS devices; MOSFETs; Stress; Voltage;
Conference_Titel :
Reliability Physics Symposium, 1993. 31st Annual Proceedings., International
Conference_Location :
Atlanta, GA, USA
Print_ISBN :
0-7803-0782-8
DOI :
10.1109/RELPHY.1993.283300
