A new CMOS circuit representation for timing verification

A structured logical circuit expression (SLICE) is proposed to unify the representation of restoring logic gate and path transistor logic, which are two major logic styles in CMOS circuit design. The SLICE representation provides a systematic way to describe signal flow in CMOS transistor networks. Timing verification can be easily performed by the SLICE representation due to its natural capacity for path enumeration and critical path analysis. Moreover, signal paths and logic stages of a CMOS circuit can be identified to facilitate efficient timing verification.<>