3D-Resurf: The integration of a p-channel LDMOS in a standard CMOS process

This paper presents an isolated high voltage (HV) p- channel lateral double diffused MOS (LDMOS) transistor integrated in a commercial 0.35mum CMOS process without any additional mask or implant steps and thus without increasing process complexity. It is shown that by the introduction of carefully controlled PWELL stripes in the drift region, an increase in breakdown voltages (V_B) of LDMOS transistors from 10 to up to 25 V can be achieved. For the huge field of power management and automotive applications this approach of integration allows optimization for multiple voltage domains and guarantees high quality levels at an economical price level.