Title :
Realistic spin-FET performance assessment for reconfigurable logic circuits
Author :
Gao, Yunfei ; Augustine, Charles ; Nikonov, Dmitri E. ; Roy, Kaushik ; Lundstrom, Mark S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
A rigorous numerical simulation of the spin field effect transistor (spinFET) is implemented. This method includes for the first time the effects of both channel spin relaxation and tunnel barriers between the source/drain and the channel. The key device metric, magnetoresistance ratio (MR), is found to be lower than earlier predictions which did not include these effects. Adjusting contact parameters and inserting tunnel barriers leads to an increased MR. Reconfigurable circuits with spinFETs shows ~7X, ~32X, and ~6X improvements in delay, power and area respectively as compared to a 15nm CMOS FPGA circuit. Moreover, when the spinFET is used as a sleep transistor, leakage is reduced by a factor of >104 in memory/logic circuits.
Keywords :
CMOS logic circuits; field effect transistors; field programmable gate arrays; magnetoresistance; semiconductor device breakdown; CMOS FPGA circuit; channel spin relaxation; contact parameter; leakage reduction; magnetoresistance ratio; memory circuit; numerical simulation; reconfigurable circuit; reconfigurable logic circuit; sleep transistor; spin field effect transistor; spin-FET performance assessment; tunnel barrier; CMOS integrated circuits; Integrated circuit modeling; Logic gates; Reconfigurable logic; Scattering; Semiconductor device modeling; Transistors;
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
DOI :
10.1109/VLSIT.2010.5556193
