An Adaptive Hardware Classifier in FPGA based-on a Cellular Compact Genetic Algorithm and Block-based Neural Network

This paper presents an adaptive/evolvable hardware architecture and its FPGA implementation. The adaptive hardware is based-on evolvable block-based neural network (BBNN) and a cellular compact genetic algorithm (CCGA). The BBNN consists of a 2-D array of modular neuron. The CCGA has a cellular-like structure. A proposed layer-based architecture provides a solution for integration between BBNN and CCGA that is suitable for hardware implementation. The implemented hardware demonstrates the completely intrinsic online evolution and adaptation in hardware without software running on microprocessors. This work contributes to the field of adaptive/evolvable hardware by proposing CCGA and a layer-based architecture for integration of BBNN and CCGA as a new kind of adaptive/evolvable hardware.