Kestrel: a programmable array for sequence analysis

Author

Hirschberg, Jeffrey D. ; Hughey, Richard ; Karplus, Kevin ; Speck, Don

Author_Institution

Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

fYear

1996

Firstpage

25

Lastpage

34

Abstract

Kestrel is a programmable linear systolic array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, and efficient communication using systolic shared registers. This paper describes Kestrel´s functional units in detail, and examines each of their effects on system performance. With prototypes currently in progress, we expect to complete a full Kestrel array, with between 512 and 1024 processing elements, by 1997

Keywords

estimation theory; parallel architectures; programmable logic arrays; systolic arrays; 8-bit word; Kestrel; functional units; programmable array; programmable linear systolic array processor; sequence analysis; single-cycle add-and-minimize instruction; system performance; systolic shared registers; Algorithm design and analysis; Computer architecture; Costs; Data analysis; Databases; Design engineering; Process design; Prototypes; Sequences; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on

Conference_Location

Chicago, IL

ISSN

2160-0511

Print_ISBN

0-8186-7542-X

Type

conf

DOI

10.1109/ASAP.1996.542798

Filename

542798