Title :
Decision Feedback Equalizer (DFE) behavioral macro model for packaging system eye diagram transient simulations
Author_Institution :
IBM Corp., Poughkeepsie, NY, USA
Abstract :
Decision Feedback Equalizer (DFE) is widely used in the high-speed packaging system as a part of receiver for recovering the signal from the distortion by the inter-symbol interference (ISI). Simulating the eye diagram at the receiver output after DFE is helpful to system designers especially in the case there is no longer an open eye diagram at the receiver input. Currently, particular simulation tools or particular algorithm implementations are required to support the modeling and simulation of the DFE function. In this paper, a DFE behavioral macro model is proposed and tested. The proposed DFE behavioral macro model is an HSPICE circuit model and can be used directly in any existing conventional HSPICE compatible transient simulation tools. We use a voltage controlled resistor and a capacitor to model the bit slicer (Symbol Detector) in DFE. The terminated ideal transmission lines with particular delays combined with voltage controlled voltage sources are used for modeling the Feedback Filter (FBF) part of DFE. The summer in DFE is modeled by Directional Junction. The proposed DFE behavioral macro model can be easily combined directly with existing receiver behavioral macro models targeting other receiver behaviors such as the Mpilog receiver model for accurate receiver input property modeling and the hyperbolic - tangent behavioral model for accurate pre-amplifier/CTLE nonlinear modeling.
Keywords :
circuit simulation; decision feedback equalisers; integrated circuit modelling; integrated circuit packaging; intersymbol interference; transient analysis; CTLE nonlinear modeling; DFE behavioral macro model; DFE function; HSPICE circuit model; HSPICE compatible transient simulation tools; Mpilog receiver model; accurate pre-amplifier; algorithm implementations; bit slicer; capacitor; decision feedback equalizer behavioral macro model; directional junction; feedback filter; high-speed packaging system; hyperbolic-tangent behavioral model; inter-symbol interference; packaging system eye diagram transient simulations; receiver behavioral macromodels; receiver output; signal recovery; symbol detector; system designers; terminated ideal transmission lines; voltage controlled resistor; voltage controlled voltage sources; Decision feedback equalizers; Integrated circuit modeling; Load modeling; Receivers; Signal analysis; Switches; Transient analysis;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-61284-497-8
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2011.5898515