Title :
A 32nm low power RF CMOS SOC technology featuring high-k/metal gate
Author :
Vandervoorn, P. ; Agostinelli, M. ; Choi, S.-J. ; Curello, G. ; Deshpande, H. ; El-Tanani, M.A. ; Hafez, W. ; Jalan, U. ; Janbay, L. ; Kang, M. ; Koh, K.J. ; Komeyli, K. ; Lakdawala, H. ; Lin, J. ; Lindert, N. ; Mudanai, S. ; Park, J. ; Phoa, K. ; Rahman,
Author_Institution :
Logic Technol. Dev. (Ltd.), Intel Corp., Hillsboro, OR, USA
Abstract :
A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achieves an fT of 420GHz. Concurrently, a low leakage 30pA/um NMOS achieves an fT of 218GHz. Deep-nwell/guard rings improves noise isolation by >50dB. High Q inductors, >7V breakdown voltage power amplifier transistors, varactors, and precision passives are also presented.
Keywords :
CMOS integrated circuits; electric breakdown; high-k dielectric thin films; low-power electronics; power amplifiers; radiofrequency integrated circuits; system-on-chip; varactors; frequency 218 GHz; frequency 420 GHz; size 32 nm; MOS devices; Noise; Power amplifiers; Radio frequency; System-on-a-chip; Transistors; Varactors;
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
DOI :
10.1109/VLSIT.2010.5556201
