IP-on-the-fly packet processing mechanism for an ATM/IP integrated switch

Author

Shimonishi, Hideyuki ; Murase, Tutomu ; Yamada, Kenji

Author_Institution

C&C Media Res. Labs., NEC Corp., Japan

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

626

Abstract

We propose a new packet processing mechanism caged IP-on-the-fly for an ATM and IP integrated switch used in IETF classical IP over ATM networks. The proposed mechanism enables ATM-based QOS control for IP traffic as well as wire-speed IP packet forwarding in the switch. One of the attractive features of this mechanism is that IP over ATM multi-layer protocol processing is logically performed in a cell-by-cell manner without packet reassembling, which contributes to the high-speed processing and cost reduction. The necessary processing mechanisms and functional configurations for the proposed mechanism are described

Keywords

asynchronous transfer mode; electronic switching systems; packet switching; quality of service; telecommunication traffic; transport protocols; ATM-based QOS control; ATM/IP integrated switch; IETF; IP over ATM networks; IP traffic; IP-on-the-fly packet processing; cost reduction; functional configurations; high-speed processing; multi-layer protocol processing; wire-speed IP packet forwarding; Asynchronous transfer mode; Bandwidth; Costs; National electric code; Packet switching; Protocols; Spine; Switches; Telecommunication switching; Telecommunication traffic;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1999. GLOBECOM '99

Conference_Location

Rio de Janeireo

Print_ISBN

0-7803-5796-5

Type

conf

DOI

10.1109/GLOCOM.1999.830128

Filename

830128