DocumentCode
1726952
Title
Novel circuit design and process technology for leading-edge products
Author
Miyamoto, K. ; Strojwas, A. ; Hosomi, E. ; Ooida, M. ; Ezawa, H. ; Fukuda, M. ; Matsubara, Y. ; Numata, K.
Author_Institution
Semicond. Co., Toshiba Corp., Kawasaki, Japan
fYear
2010
Firstpage
141
Lastpage
142
Abstract
Achieving power, performance, yield and cost scaling targets at leading edge technology nodes has become significantly more challenging. Success is driven by making the optimal combination of process, design, and package decisions. In this paper, we report novel circuit design and process technologies for leading-edge products. We focus on two topics: (1) chip design optimization using extremely regular layout methodology, and (2) SiP (System in Package) with CoC (chip on chip) for 40nm technology node products.
Keywords
integrated circuit design; system-in-package; chip design optimization; chip on chip; circuit design; cost scaling; extremely regular layout methodology; leading-edge products; package decisions; process technology; system in package; Fabrics; Layout; Libraries; Logic gates; Random access memory; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location
Honolulu
Print_ISBN
978-1-4244-5451-8
Electronic_ISBN
978-1-4244-5450-1
Type
conf
DOI
10.1109/VLSIT.2010.5556203
Filename
5556203
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