Development of Super Thin TSV PoP

One of the hottest topics in the semiconductor industry today is a 3D packaging using Through Silicon Via (TSV) technology. Driven by the need for improved electrical performance or the reduction of timing delays, methods to use short vertical interconnects have been developed to replace the long interconnects found in 2D packaging. 3D TSV interposer is an efficient and practical approach to solving die integration challenges. Many microsystem devices that will have to move to wafer-level packages will also facilitate further integration using silicon TSV interposers. This paper will address TSV interposer development for mobile applications to replace normal organic laminate substrate. Major driver of this work is for PoP thickness reduction since current organic PoP is one of the thickest components in cellular phone engine. Super Thin PoP test vehicle was designed in order to prove the viability of this technology. This test vehicle was a 12×12mm package with 0.4mm ball pitch on the bottom and 0.4mm pitch between the top and bottom PoP package. Test vehicle has 0.1mm thick TSV substrate and bare-die flip-chip, achieving 0.7mm total stackup height vs. equivalent organic PoP of ~1.5mm. This paper will highlight the TSV interposer test vehicle design, fabrication, assembly process development, warpage behavior study with simulation and experiments, component level reliability test results of the Super Thin PoP test vehicle and future steps.