DocumentCode :
1727098
Title :
Design, simulation and process optimization of AuInSn low temperature TLP bonding for 3D IC Stacking
Author :
Xie, Ling ; Choi, Won Kyoung ; Premachandran, C.S. ; Selvanayagam, Cheryl S. ; Bai, Ke Wu ; Zeng, Ying Zhi ; Ong, Siong Chiew ; Liao, Ebin ; Khairyanto, Ahmad ; Sekhar, V.N. ; Thew, Serene
Author_Institution :
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear :
2011
Firstpage :
279
Lastpage :
284
Abstract :
An IMC based low temperature solder <;200°C with AuInSn composition is developed for 3D IC stacking application. Thermodynamic and mechanical simulations are conducted to study the phase change during the melting temperature and the stress due to the thin solder material. A three layer stack bonding with the developed solder has been characterized after bonding and reliability test. It is found that no degradation in shear strength and compositional structure of the solder and is verified by the TEM cross sectional structure with EDX analysis. A 3D IC structure with TSV test vehicle is designed and demonstrated the low temperature solder application. C2W bonding approach is used for the 3D IC stack bonding method and is found suitable for devices with TSV structure. Final reliability test with daisy chain structure and TSV showed <;10% resistance increase in majority of interconnections after 1000 cycles of thermal cycle test.
Keywords :
X-ray chemical analysis; bonding processes; gold alloys; indium alloys; integrated circuit interconnections; integrated circuit reliability; solders; stacking; three-dimensional integrated circuits; tin alloys; transmission electron microscopy; 3D IC stacking; AuInSn; AuInSn composition; EDX analysis; TEM cross sectional structure; interconnections; low temperature TLP bonding; low temperature solder; mechanical simulation; melting temperature; process optimization; reliability; shear strength; thermodynamic simulation; thin solder material; transient liquid phase; Bonding; Copper; Gold; Joints; Stress; Through-silicon vias; Vehicles;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
Conference_Location :
Lake Buena Vista, FL
ISSN :
0569-5503
Print_ISBN :
978-1-61284-497-8
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2011.5898526
Filename :
5898526
Link To Document :
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