Title :
Integration of Back-Gate doping for 15-nm node floating body cell (FBC) memory
Author :
Ban, Ibrahim ; Avci, Uygar E. ; Kencke, David L. ; Tolchinsky, Peter ; Chang, Peter L D
Author_Institution :
Components Res., Intel Corp., Hillsboro, OR, USA
Abstract :
Key process features of a scaled, high-performance planar FBC memory fabricated on 25-nm undoped Si and 10-nm BOX SOI substrates are presented. Back-Gate (BG) doping process is revealed to be a critical part of the FBC integration. BG dopant loss due to oxidation and high-temperature processes is minimized to enable high performance at scaled diffusion widths (W<;100 nm). Integrating BG doping processes and designing tips and source/drain, we demonstrate a memory retention of over 1 sec (@ 3-μA sensing window) in scaled cells (Lg=50 nm, W=85 nm) suitable for 15-nm technology node.
Keywords :
semiconductor doping; silicon-on-insulator; storage management chips; BG dopant loss; BOX SOI substrates; back-gate doping process integration; floating body cell memory; high temperature processes; high-performance planar FBC memory; oxidation; size 10 nm; size 15 nm; size 25 nm; source-drain design; Annealing; Doping; Implants; International Electron Devices Meeting; Logic gates; Performance evaluation; Substrates;
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
DOI :
10.1109/VLSIT.2010.5556210
