The CSI chip - a CMOS charge successive integrator with wide dynamic range for the telescope array project

A charge successive integrator (CSI) VLSI with wide dynamic range has been developed for front-end electronics of the Telescope Array project. The CSI has more than 14-bit dynamic range and successively integrate the charge from photo-multiplier tube every 200ns. We have newly designed offset-compensated charge integrator to reduce the offset voltage and the 1/f noise. We expect that the offset voltage and the maximum 1/f noise can be reduced to less than 1mV and 5mV respectively with this technique. The prototype CSI chip was fabricated in a 0.6μm commercially available CMOS technology. The test results of the prototype CSI chip, which has no offset compensation, are compared to the offset-compensated low-1/f noise CSI to confirm the effectiveness of this technique.