Prediction of ESD robustness in a process using 2D device simulations

The use of 2D device simulations in predicting the ESD robustness of MOS devices is discussed. The merits of using the peak power density, JE, and the second breakdown trigger current, I/sub t2/, as a measure of the relative robustness of MOS devices with varying drain/source profiles, contact to gate spacing, and gate bias conditions, is studied. It is shown that the peak JE correlates with the peak temperature in the device, but it is strongly influenced by variations in the grid. Hence, its applicability is limited to comparing the relative robustness of devices with simulations where the grid does not change drastically. I/sub t2/ is less sensitive to grid variations and is more widely applicable for analyzing the effect of technology variations on ESD robustness.<>