DocumentCode :
172742
Title :
An adaptive detector implementation for MIMO-OFDM downlink
Author :
Shahabuddin, S. ; Janhunen, Janne ; Suikkanen, Essi ; Steendam, Heidi ; Juntti, Markku
Author_Institution :
Dept. of Commun. Eng., Univ. of Oulu, Oulu, Finland
fYear :
2014
fDate :
2-4 June 2014
Firstpage :
305
Lastpage :
310
Abstract :
Cognitive radio (CR) systems require flexible and adaptive implementations of signal processing algorithms. An adaptive symbol detector is needed in the baseband receiver chain to achieve the desired flexibility of a CR system. This paper presents a novel design of an adaptive detector as an application-specific instruction-set processor (ASIP). The ASIP template is based on transport triggered architecture (TTA). The processor architecture is designed in such a manner that it can be programmed to support different suboptimal multiple-input multiple-output (MIMO) detection algorithms in a single TTA processor. The linear minimum mean-square error (LMMSE) and three variants of the selective spanning for fast enumeration (SSFE) detection algorithms are considered. The detection algorithm can be switched between the LMMSE and SSFE according to the bit error rate (BER) performance requirement in the TTA processor. The design can be scaled for different antenna configurations and different modulations. Some of the algorithm architecture co-optimization techniques used here are also presented. Unlike most other detector ASIPs, high level language is used to program the processor to meet the time-to-market requirements. The adaptive detector delivers 4.88-49.48 Mbps throughput at a clock frequency of 200 MHz on 90 nm technology.
Keywords :
MIMO communication; OFDM modulation; cognitive radio; error statistics; instruction sets; mean square error methods; radio links; radio receivers; signal processing; ASIP template; BER; CR systems; LMMSE; MIMO detection algorithms; MIMO-OFDM downlink; SSFE detection algorithms; TTA processor; adaptive detector implementation; adaptive symbol detector; application specific instruction set processor; baseband receiver chain; bit error rate; cognitive radio; cooptimization techniques; linear minimum mean-square error; multiple-input multiple-output; processor architecture; selective spanning for fast enumeration; signal processing algorithms; transport triggered architecture; Bit error rate; Clocks; Detection algorithms; Detectors; Matrix decomposition; Throughput; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Cognitive Radio Oriented Wireless Networks and Communications (CROWNCOM), 2014 9th International Conference on
Conference_Location :
Oulu
Type :
conf
Filename :
6849703
Link To Document :
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