Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO₂ interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO₂ interface and Vt = -0.20 V consistent with a PMOS EWF =5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO₂ interface that play a critical role in determining the PMOS EWF.