Author :
Ortolland, C. ; Sahhaf, S. ; Srividya, V. ; Degraeve, R. ; Saino, K. ; Kim, C.S. ; Gilbert, M. ; Kauerauf, T. ; Cho, M.J. ; Dehan, M. ; Schram, T. ; Togo, M. ; Horiguchi, N. ; Groeseneken, G. ; Biesemans, S. ; Absil, P.P. ; Vandervorst, W. ; Gealy, D. ; H
Abstract :
This paper demonstrates for the first time a low cost, low complexity process CMOS Hk/MG for low-power applications with Vth controlled by gate Ion-Implantation (I/I) and High-k capping for NMOS and PMOS, respectively. Novel advanced electrical and physical characterizations provide unique insights about the underlying mechanism of Vth adjust induced by I/I into the metal. Improved RO performance, with excellent uniformity and matching characteristics have been achieved without reliability degradation.
Keywords :
CMOS integrated circuits; circuit complexity; high-k dielectric thin films; ion implantation; low-power electronics; NMOS; PMOS; gate ion implantation; high-k capping; low cost low complexity process; low power CMOS; low-cost high k-metal gate process; reliability degradation; Argon; CMOS integrated circuits; Implants; Logic gates; MOS devices; Metals; Silicon;
