Direct observation of RTN-induced SRAM failure by accelerated testing and its application to product reliability assessment

Author

Takeuchi, K. ; Nagumo, T. ; Takeda, K. ; Asayama, S. ; Yokogawa, S. ; Imai, K. ; Hayashi, Y.

Author_Institution

LSI Fundamental Res. Lab., NEC Electron. Corp., Sagamihara, Japan

fYear

2010

Firstpage

189

Lastpage

190

Abstract

A new accelerated testing scheme for detecting SRAM bit failure caused by random telegraph noise (RTN) is proposed. By repeatedly monitoring the fail bit count (FBC) under a reduced margin operation condition, increasing trend of FBC along time was clearly observed, which is believed to be caused by RTN. In addition, physics-based ultra-fast Monte Carlo RTN simulation program has been developed, which quantitatively reproduces the test results. By using the simulation calibrated by the test, product reliability against RTN can be accurately predicted.

Keywords

Monte Carlo methods; SRAM chips; integrated circuit noise; integrated circuit reliability; integrated circuit testing; life testing; random noise; RTN; SRAM bit failure; accelerated testing; fail bit count; product reliability assessment; random telegraph noise; reduced margin operation; ultrafast Monte Carlo simulation; FETs; Fluctuations; Life estimation; Noise; Random access memory; Resource description framework; Semiconductor process modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2010 Symposium on

Conference_Location

Honolulu

Print_ISBN

978-1-4244-5451-8

Electronic_ISBN

978-1-4244-5450-1

Type

conf

DOI

10.1109/VLSIT.2010.5556222

Filename

5556222