DocumentCode :
1727608
Title :
Programming disturbance and cell scaling in phase change memory: For up to 16nm based 4F2 cell
Author :
Lee, S.H. ; Kim, M.S. ; Do, G.S. ; Kim, S.G. ; Lee, H.J. ; Sim, J.S. ; Park, N.G. ; Hong, S.B. ; Jeon, Y.H. ; Choi, K.S. ; Park, H.C. ; Kim, T.H. ; Lee, J.U. ; Kim, H.W. ; Choi, M.R. ; Lee, S.Y. ; Kim, Y.S. ; Kang, H.J. ; Kim, J.H. ; Kim, H.J. ; Son, Y.S.
Author_Institution :
Device & PI Technol. Group, Hynix Semicond. Inc., Icheon, South Korea
fYear :
2010
Firstpage :
199
Lastpage :
200
Abstract :
We focus here on the promising solutions to overcome thermal-induced erase failure of the unselected neighbor cell while a selected cell is being programmed to reset state with a high-current pulse. Our physical analysis directly demonstrate that this parasitic heating in Ge2Sb2Te5 based cell leads to partial crystallization in the amorphous reset state and to a consequent resistance decrease with disturbing current. Systematic approaches compatible with disturbance-free are addressed to achieve a highly scalable architecture, which can provide the physical and electrical criteria for phase change memory (PCM) up to 16nm technology node.
Keywords :
antimony compounds; germanium compounds; phase change memories; Ge2Sb2Te5; amorphous reset state; cell scaling; parasitic heating; phase change memory; programming disturbance; selected cell; size 16 nm; thermal-induced erase failure; unselected neighbor cell; Computer architecture; Microprocessors; Phase change materials; Programming; Space technology; Thermal resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location :
Honolulu
Print_ISBN :
978-1-4244-5451-8
Electronic_ISBN :
978-1-4244-5450-1
Type :
conf
DOI :
10.1109/VLSIT.2010.5556226
Filename :
5556226
Link To Document :
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