DocumentCode
1727631
Title
MLC PRAM with SLC write-speed and robust read scheme
Author
Hwang, Y.N. ; Um, C.Y. ; Lee, J.H. ; Wei, C.G. ; Oh, H.R. ; Jeong, G.T. ; Jeong, H.S. ; Kim, C.H. ; Chung, C.H.
Author_Institution
New Memory Lab., Samsung Electron. Co., Ltd., Hwasung, South Korea
fYear
2010
Firstpage
201
Lastpage
202
Abstract
We have proposed an integrated method to realize MLC PRAM at 45 nm technology node and beyond. It includes reset initialization, Toff skew write, and 2bit write to enhance write-and-verify speed, and 3-cell reference scheme to cope with cell variation due to resistance drift and temperature change. Based on the proposed methods, write throughput can be increased up to SLC level with robust read operation.
Keywords
random-access storage; 3-cell reference scheme; MLC PRAM; SLC write-speed scheme; Toff skew write; cell variation; resistance drift; robust read scheme; size 45 nm; write throughput; write-and-verify speed enhancement; Computer architecture; Microprocessors; Phase change random access memory; Resistance; Temperature sensors; Throughput; MLC; PRAM; reference cell; speed;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2010 Symposium on
Conference_Location
Honolulu
Print_ISBN
978-1-4244-5451-8
Electronic_ISBN
978-1-4244-5450-1
Type
conf
DOI
10.1109/VLSIT.2010.5556227
Filename
5556227
Link To Document