Title :
High Voltage P-Channel MOS Breakdown Voltage Instability During High Temperature Gate Stress Induced by Pre-Metal Nitride Layers
Author :
Marchesi, G. ; Cambieri, J. ; Dundulachi, A. ; Pizzo, G. ; Pozzobon, F. ; Annese, M. ; Andreini, A. ; Croce, G.
Author_Institution :
STMicroelectronics, FTM R&D, Milan
Abstract :
An anomalous breakdown voltage degradation has been observed during high temperature gate stress (HTGS) test on 20 V double diffused drain (DDD) P-channel device realized on a 0.18 mum high voltage gate (HVG) platform. The critical role played by the salicide protection and borderless nitride layers has been pointed out by dedicated process trials.
Keywords :
MOS integrated circuits; electric breakdown; breakdown voltage degradation; double diffused drain; high temperature gate stress; high voltage P-channel MOS breakdown voltage instability; premetal nitride layer; size 0.18 mum; voltage 20 V; Breakdown voltage; Degradation; Displays; Driver circuits; Kinetic theory; MOS devices; Protection; Stress; Temperature; Testing;
Conference_Titel :
Power Semiconductor Devices and IC's, 2008. ISPSD '08. 20th International Symposium on
Conference_Location :
Orlando, FL
Print_ISBN :
978-1-4244-1532-8
Electronic_ISBN :
978-1-4244-1533-5
DOI :
10.1109/ISPSD.2008.4538952
