Multi-objective optimization of microprocessor package vertical interconnects

The parameterization and optimization of multi-layered vertical interconnect structures can enable the successful electrical design of high-performance microprocessor packages as signaling rates and density are scaled aggressively. Improved bandwidth can also translate into lower cost through layer count reduction, smaller package size and use of standard materials. A framework built around rapid full-wave electromagnetic solution to enable parametrics and optimization is critical in order to achieve this objective. In this work, a full-wave solver based trade-off generation methodology is developed. This trade-off technique permits the exploration of return loss and crosstalk of realistic complex vertical interconnect structures. The parameterization routine includes arbitrarily placed non-uniform vertical vias, voids, and differential high-speed lines. Overall computation time is made tractable by the use of an accelerated full-wave solver engine. The hierarchical response surface based optimization approach [1] is built upon and expanded for simultaneous return loss and crosstalk optimization, respectively. Weighted sum and adaptive weighted sum methods are used to conduct multi-objective optimization and find the Pareto front. Optimized designs are found to have both significantly improved differential return loss and crosstalk characteristics over high-speed channel frequency bands of interest.