• DocumentCode
    1727881
  • Title

    Design challenges and enablement for 28nm and 20nm technology nodes

  • Author

    Hou, Cliff Yung-Chin

  • Author_Institution
    Design & Technol. Platform, R&D, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
  • fYear
    2010
  • Firstpage
    225
  • Lastpage
    226
  • Abstract
    This paper presents technology and design challenges at 28nm and 20nm technology nodes, and provides solutions as key enablement for designers to effectively overcome those challenges.
  • Keywords
    integrated circuit design; integrated circuit layout; integrated circuit technology; nanotechnology; IP design; design challenges; layout dependent effect; size 20 nm; size 28 nm; IP networks; Layout; Logic gates; Metals; Silicon; Technological innovation; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology (VLSIT), 2010 Symposium on
  • Conference_Location
    Honolulu
  • Print_ISBN
    978-1-4244-5451-8
  • Electronic_ISBN
    978-1-4244-5450-1
  • Type

    conf

  • DOI
    10.1109/VLSIT.2010.5556237
  • Filename
    5556237
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1727881