• DocumentCode
    1728009
  • Title

    Analyze the behavior model based on Verilog-A for Sallen-Key low-pass filter

  • Author

    Po-Yu Kuo ; Liao-Fong Sie

  • Author_Institution
    Dept. of Electron. Eng., Nat. Yunlin Univ. of Sci. & Technol., Doulou, Taiwan
  • fYear
    2015
  • Firstpage
    460
  • Lastpage
    461
  • Abstract
    To design an analog circuit, most designers analyze the circuit performance using Hspice. However, if the circuit scale is large, it will consume a lot of time to finish the simulations. In this paper, the behavior model of a Sallen-Key low-pass filter is analyzed based on Verilog-A. The behavior model has been applied to simulate the cutoff frequency and the total output noise. The error of simulation results from Verilog-A is less that 4% compared to the results from Hspice. Moreover, Verilog-A simulate the results in less computation time compared with Hspice.
  • Keywords
    active filters; analogue circuits; hardware description languages; low-pass filters; network analysis; Sallen-Key low-pass filter; Verilog-A; analog circuit design; cut-off frequency; total output noise;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics - Taiwan (ICCE-TW), 2015 IEEE International Conference on
  • Conference_Location
    Taipei
  • Type

    conf

  • DOI
    10.1109/ICCE-TW.2015.7216998
  • Filename
    7216998