• DocumentCode
    1728071
  • Title

    Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias

  • Author

    Sukumaran, Vijay ; Bandyopadhyay, Tapobrata ; Chen, Qiao ; Kumbhat, Nitesh ; Liu, Fuhan ; Pucha, Raghu ; Sato, Yoichiro ; Watanabe, Mitsuru ; Kitaoka, Kenji ; Ono, Motoshi ; Suzuki, Yuya ; Karoui, Choukri ; Nopper, Christian ; Swaminathan, Madhavan ; Sund

  • Author_Institution
    3D Syst. Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    2011
  • Firstpage
    583
  • Lastpage
    588
  • Abstract
    This paper demonstrates thin glass interposers with fine pitch through package vias (TPV) as a low cost and high I/O substrate for 3D integration. Interposers for packaging of ULK and 3D-ICs need to support large numbers of die to die interconnections with I/O pitch below 50 μm. Current organic substrates are limited by CTE mismatch, wiring density, and poor dimensional stability. Wafer based silicon interposers can achieve high I/Os at fine pitch, but are limited by high cost. Glass is an ideal interposer material due to its insulating property, large panel availability and CTE match to silicon. The main focus of this work is on a) electrical and mechanical design, b) TPV and fine line formation and c) integration process and electrical characterization of thin glass interposers. This work for the first time demonstrates high throughput formation of 30 μm pitch TPVs in ultrathin glass using a parallel laser process. An integration process was demonstrated for glass interposer with polymer build-up layers on both sides. The glass interposer had stable electrical properties up to 20GHz and low insertion loss of less than 0.15dB was measured for TPVs at 9GHz.
  • Keywords
    fine-pitch technology; glass; integrated circuit interconnections; three-dimensional integrated circuits; 3D integration; 3D-IC; CTE mismatch; TPV; ULK packaging; current organic substrate; fine-pitch through-package-vias; frequency 9 GHz; high I/O substrate; low-cost glass interposers; parallel laser process; polymer build-up layers; thin glass interposer; wafer based silicon interposer; wiring density; Copper; Glass; Polymers; Stress; Substrates; Wiring; Electrical design; Glass interposer; fine line wiring; laser ablation; mechanical modeling; through package via;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-61284-497-8
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2011.5898571
  • Filename
    5898571