Package-Interposer-Package (PIP): A breakthrough Package-on-Package (PoP) technology for high end electronics

This paper discusses a new 3D “Package-Interposer-Package” (PIP) solution suitable for combining multiple memory, ASICs, stacked die, stacked packaged die, etc., into a single package. Recent work on interposers to join multiple packages is highlighted, with particular attention paid to the processing of the electrical joints formed between the interposer and package. A variety of package-interposer-package joining approaches were considered. Photographs were used to investigate the joining, conducting mechanism and path. Traditional Package-on-Package (PoP) approaches use direct solder connections between the packages and are limited to use of single (or minimum) die in the bottom package(s) in order to avoid warpage and poor reliability performance. This is because each package may have a different warpage trend from room temperature to reflow temperature when combined with other packages. For PIP, the stability imparted by the interposer reduces warpage and increases stability, allowing assemblers of the PIP to select the top and bottom components (packages, dies, stacked die, modules) from various suppliers. PIP can accommodate multiple stacks of dies. PIP can use modules with stacked die where modules can be organic, ceramic, or silicon board, where each can be detached and replaced without affecting the rest of the package. Thus PIP will be economical for high-end electronics, where a damaged, non-functional part of the package can be selectively removed and replaced. The paper also describes interconnect construction for a PIP. The present process allows fabrication of PIP interconnect joints having diameters in the range of 55-300 microns, allowing finer pitch, higher density packaging structures. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.