DocumentCode
1728432
Title
Using UML Sequence Diagrams and State Machines for Test Input Generation
Author
Bandyopadhyay, Aritra ; Ghosh, Sudipto
Author_Institution
Dept. of Comput. Sci., Colorado State Univ., Fort Collins, CO
fYear
2008
Firstpage
309
Lastpage
310
Abstract
We present a novel testing approach that combines information from UML sequence models and state machine models. We use sequence models to extract message paths that play a role in critical usage scenarios of a system. We use state machines to generate multiple execution paths from a message path by analyzing the effect of the messages on state transitions of the system. By covering these execution paths, we generate more effective test cases than the approaches that only cover message paths. The approach also reduces the number of state transitions to be tested by selecting only those that are fired in critical scenarios.
Keywords
Unified Modeling Language; finite state machines; message passing; program testing; UML sequence diagrams; UML sequence models; message paths; multiple execution paths; state machine models; state machines; state transitions; test input generation; testing approach; Collaboration; Computer science; Data mining; Engineering students; Knowledge engineering; Software reliability; Software testing; System testing; Unified modeling language; class diagrams; model-based testing; sequence diagrams; state machine diagrams; test input generation;
fLanguage
English
Publisher
ieee
Conference_Titel
Software Reliability Engineering, 2008. ISSRE 2008. 19th International Symposium on
Conference_Location
Seattle, WA
ISSN
1071-9458
Print_ISBN
978-0-7695-3405-3
Electronic_ISBN
1071-9458
Type
conf
DOI
10.1109/ISSRE.2008.16
Filename
4700350
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