Title :
Submicron CMOS transient test structure for low power VLSI
Author_Institution :
Dept. of Inf. & Commun. Eng., Dongshin Univ., Chonnam, South Korea
Abstract :
A process patterning test structure with analog and digital circuits which contain gate-width (WG) and gate-length (LG) combination is designed and fabricated for transient/AC performance verifications. Ultra-low power was observed from arrow gate-width and larger drain length test structure with same gate-length at various voltages, resulting in 10 nA at 1 V and 0.15 mA at 5 V for a WG/LG=1 μm/20 μm CMOS ring oscillator because of high threshold voltage and low sleep-mode control though speed tradeoff due to low threshold voltage and high sleep-mode control is insignificant. Hence narrow, but properly optimized gate-width, and large drain length test structure at designated CMOS technology is promising for upcoming VLSI/USLI analog/digital low power designs
Keywords :
CMOS analogue integrated circuits; CMOS integrated circuits; VLSI; integrated circuit testing; transient analysis; 1 micron; 1 to 5 V; 10 nA to 0.15 mA; 20 micron; AC performance; analog circuit; digital circuit; drain length; gate length; gate width; low power VLSI; process patterning; ring oscillator; sleep-mode control; submicron CMOS transient test structure; threshold voltage; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS process; CMOS technology; Circuit testing; Low voltage; Microelectronics; Threshold voltage; Very large scale integration; Voltage control;
Conference_Titel :
Microelectronics, 1997. Proceedings., 1997 21st International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-3664-X
DOI :
10.1109/ICMEL.1997.632956
