DocumentCode
1728833
Title
32-bit High Performance Embedded Microprocessor
Author
Wenxin, Qu ; Xiaoya, Fan ; Ying, Hu
Author_Institution
Northwestern Polytech Univ., Xi´´an
fYear
2007
Abstract
The Aviation Microelectronic Center of NPU (Northwestern Polytechnical University) has recently completed the development of a 32-bit super-scalar RISC microprocessor, called "Longtium" R2. In this paper the architecture of "Longtium" R2 is presented. Firstly, the whole architecture of the "Longtium" R2 microprocessor is presented. Gives the schematic diagram of the architecture of the "Longtium" R2. Then the design and implement are discussed. The "Longtium" R2 CPU is fabricated in a 0.18 mum CMOS process. The die size of the chip is 4.1 mm times 5.2 mm and the CPU operating frequency is at least 233 MHz .
Keywords
CMOS digital integrated circuits; microprocessor chips; reduced instruction set computing; Aviation Microelectronic Center; CMOS process; Longtium R2 microprocessor; Northwestern Polytechnical University; embedded microprocessor; high performance microprocessor; size 0.18 mum; super-scalar RISC microprocessor; word length 32 bit; Access protocols; CMOS process; Decoding; Frequency; Instruments; Memory management; Microelectronics; Microprocessors; Reduced instruction set computing; Registers; Longtium; RISC; microprocessor;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Measurement and Instruments, 2007. ICEMI '07. 8th International Conference on
Conference_Location
Xi´an
Print_ISBN
978-1-4244-1136-8
Electronic_ISBN
978-1-4244-1136-8
Type
conf
DOI
10.1109/ICEMI.2007.4350888
Filename
4350888
Link To Document