DocumentCode :
1729056
Title :
Efficent low cost process for single step metal forming of 3D interconnected above-IC inductors
Author :
Ghannam, Ayad ; Ourak, Lamine ; Bourrier, David ; Viallon, Christophe ; Parra, Thierry
Author_Institution :
LAAS, CNRS, Toulouse, France
fYear :
2011
Firstpage :
367
Lastpage :
370
Abstract :
This paper presents a novel and efficient low cost process capable of integrating high-Q above-IC inductors and their interconnects using a single electroplating step. It relies on the SU8 and BPN resist as well as an optimized electroplating technique to form the 3D interconnected inductor. The SU8 is used to form a thick layer located underneath the inductor to elevate it from the substrate. Then, the BPN is used as a high resolution mold (16:1) for copper electroplating. Standard or time optimized electroplating is later used to grow copper in a 3D manner, making the transition between all metallic layers straight forward. High-Q (55 @ 5 GHz) power inductors have been designed and integrated above an RF power LDMOS device using this process. Finally, the process capabilities are demonstrated by integrating a solenoid inductor using only two lithography masks and a single electroplating step.
Keywords :
electroplating; integrated circuit interconnections; integrated circuits; power inductors; solenoids; 3D interconnected above-IC inductors; BPN; RF power LDMOS device; frequency 5 GHz; high resolution mold; lithography masks; low cost process; power inductors; single copper electroplating step; single step metal; solenoid inductor; Copper; Dielectrics; Inductors; Radio frequency; Resists; Substrates; Three dimensional displays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European
Conference_Location :
Helsinki
ISSN :
1930-8876
Print_ISBN :
978-1-4577-0707-0
Electronic_ISBN :
1930-8876
Type :
conf
DOI :
10.1109/ESSDERC.2011.6044158
Filename :
6044158
Link To Document :
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