Development of Si interposer with low inductance decoupling capacitor

In order to realize high-performance LSI systems, a Si interposer with Cu filled through silicon vias (TSVs) and a low inductance decoupling capacitor was developed in this work. We fabricated a thin film capacitor (TFC) on the Si interposer and evaluated its properties. Capacitance density of the TFC achieved 2uF/cm². Temperature coefficient of capacitance (TCC) was under 15% (25-125 deg C). The leakage current at 3V was below 1nA up to 100 deg C. The effect of TFC´s location on impedance was measured. The interposer had lower impedance in case of the TFC embedded close to LSI. This enabled decreasing the impedance at high frequency range. Inductance values and an impedance curve of the Si interposer with the embedded multi-terminal TFC were also evaluated. As increasing number of the terminals, the inductance was decreased, and the impedance curve was declined over a wide frequency range. Finally, based on these technologies described above, we have fabricated a prototype of Si interposer. The embedded TFC is effective to minimize the impedance of power delivery network (PDN) at high frequencies. This Si interposer can improve the characteristics of LSI systems.