Gold-doped high resistivity Czochralski-silicon for integrated passive devices and 3D integration

Author

Abuelgasim, Ahmed ; Mallik, Kanad ; de Groot, C.H. ; Ashburn, P.

Author_Institution

Sch. of Electron. & Comput. Sci., Univ. of Southampton, Southampton, UK

fYear

2011

Firstpage

363

Lastpage

366

Abstract

We show that deep level doping of Czochralski-grown silicon wafers is capable of providing very high resistivity wafers suitable for integrated passive devices and 3D integration. Starting from n-type Czochralski silicon wafers having a nominal resistivity of 50 Ωcm, we use Au ion implantation to increase the resistivity. Coplanar waveguides fabricated on the wafers show strongly reduced attenuation. Hall measurements indicate that the increase in resistivity is clearly due to a reduction in free carriers. The temperature dependence of the free carrier concentration in the range of 200-350K indicates that the Fermi-level is virtually pinned mid-gap.

Keywords

Fermi level; Hall effect; carrier density; coplanar waveguides; crystal growth from melt; deep levels; electrical resistivity; elemental semiconductors; gold; ion implantation; passive networks; semiconductor doping; silicon; three-dimensional integrated circuits; 3D integration; Fermi-level; Hall measurements; Si:Au; coplanar waveguides; deep level doping; free carrier concentration; gold-doped high resistivity Czochralski-silicon; high resistivity wafers; integrated passive devices; ion implantation; n-type Czochralski silicon wafers; temperature 200 K to 350 K; virtually pinned mid-gap; Attenuation; Conductivity; Gold; Inductors; Silicon; Spirals; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European

Conference_Location

Helsinki

ISSN

1930-8876

Print_ISBN

978-1-4577-0707-0

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2011.6044159

Filename

6044159