A 9.6 GigaByte/s throughput plesiochronous routing chip

Author

Mu, A. ; Larson, J. ; Sastry, R. ; Wicki, T. ; Wilcke, W.W.

Author_Institution

HAL Computer Systems Inc., Campbell, CA, USA

fYear

1996

Firstpage

261

Lastpage

266

Abstract

The design of a very high performance routing chip with six bi-directional link ports and an aggregate sustained throughput of 9.6 GByte/s is described The routing chips will form the switching fabric of a cache-coherent, Non-Uniform Memory Access (cc-NUMA) multiprocessor system. The key elements of the chip are a non-blocking internal crossbar; synchronization circuits for plesiochronous operation (i.e. no central system clock required) and reliance on hardware end-to-end error checking. The chip has recently been taped out.

Keywords

multiprocessing systems; multiprocessor interconnection networks; network routing; packet switching; parallel architectures; synchronisation; 9.6 GB/s; HAL multiprocessor system; bi-directional link ports; cache-coherent nonuniform memory access multiprocessor system; cc-NUMA multiprocessor system; hardware end-to-end error checking; nonblocking internal crossbar; plesiochronous routing chip; synchronization circuits; very high performance routing chip; Aggregates; Bidirectional control; Circuits; Clocks; Fabrics; Hardware; Multiprocessing systems; Routing; Synchronization; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon '96. 'Technologies for the Information Superhighway' Digest of Papers

Conference_Location

Santa Clara, CA, USA

ISSN

1063-6390

Print_ISBN

0-8186-7414-8

Type

conf

DOI

10.1109/CMPCON.1996.501780

Filename

501780