DocumentCode :
1729585
Title :
An investigation on steep-slope and low-power nanowire FETs
Author :
Gnani, E. ; Maiorano, P. ; Reggiani, S. ; Gnudi, A. ; Baccarani, G.
Author_Institution :
DEIS, Univ. of Bologna, Bologna, Italy
fYear :
2011
Firstpage :
299
Lastpage :
302
Abstract :
In this work we investigate by numerical simulation the achievable performance of a steep-slope nanowire FET based on the filtering of the high-energy electrons by a superlattice heterostructure in the source extension. After a preliminary study aimed to identify the most promising material pairs for the superlattice with respect to the typical FET evaluation metrics, we concentrate on a superlattice-based FET employing the InGaAs-InAlAs pair, which provides a good switching slope and an excellent on-current. The device optimization leads to a prediction of an inverse SS = 35 mV/dec and an on-current exceeding 2.3 mA/μm at a supply voltage of 400 mV.
Keywords :
field effect transistors; low-power electronics; nanowires; FET evaluation metrics; InGaAs-InAlAs pair; device optimization; high-energy electrons; low-power nanowire FET; numerical simulation; steep-slope nanowire FET; superlattice heterostructure; superlattice-based FET; FETs; Indium gallium arsenide; Logic gates; Superlattices; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European
Conference_Location :
Helsinki
ISSN :
1930-8876
Print_ISBN :
978-1-4577-0707-0
Electronic_ISBN :
1930-8876
Type :
conf
DOI :
10.1109/ESSDERC.2011.6044175
Filename :
6044175
Link To Document :
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