Title :
Flip chip bonding reliability of advanced glass ceramic chip size package
Author :
Hazeyama, Ichiro ; Ikuina, Kazuhiro ; Kimura, Mitsuru ; Shimada, Yuzo
Author_Institution :
Mater. Dev. Center, NEC Corp., Kanagawa, Japan
Abstract :
In order to realize high-density wiring and to increase the reliability of chip interconnection to printed wiring boards (PWBs), we have developed glass ceramic chip size packages (CSPs). A 64M-DRAM chip was connected to the glass ceramic substrate via Au bumps by a flip chip bonding technique with high interconnection reliability, and the substrate was mounted on a PWB via solder ball bumps. To evaluate the reliability of the glass ceramic CSP, a thermal stress simulation was performed and the analysis indicated that thin glass ceramic CSPs were highly reliable. This finding was supported by thermal cycle testing using actual glass ceramic CSPs and identically structured alumina CSPs. The thin glass ceramic CSPs passed 1000 cycles, although failures were detected on the alumina CSPs between 500 and 1000 cycles. These failures were analyzed and it was confirmed that fatigue fractures occurred in the solder ball bumps due to coefficient of thermal expansion (CTE) mismatch and substrate rigidity
Keywords :
DRAM chips; chip scale packaging; failure analysis; fatigue cracks; flip-chip devices; glass ceramics; integrated circuit bonding; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; shear modulus; soldering; stress analysis; thermal analysis; thermal expansion; thermal stresses; 64 Mbit; Au; Au bumps; DRAM chip; PWBs; alumina CSPs; chip interconnection reliability; coefficient of thermal expansion mismatch; failure detection; fatigue fractures; flip chip bonding reliability; flip chip bonding technique; glass ceramic CSPs; glass ceramic chip size package; high-density wiring; interconnection reliability; printed wiring boards; solder ball bumps; substrate rigidity; thermal cycle testing; thermal stress simulation; Analytical models; Bonding; Ceramics; Chip scale packaging; Flip chip; Glass; Gold; Performance evaluation; Thermal stresses; Wiring;
Conference_Titel :
IEMT/IMC Symposium, 2nd 1998
Conference_Location :
Tokyo
Print_ISBN :
0-7803-5090-1
DOI :
10.1109/IEMTIM.1998.704624
