DocumentCode :
1729803
Title :
Improved extraction of GIDL in FDSOI devices for proper junction quality analysis
Author :
Xu, C. ; Batude, P. ; Romanjek, K. ; Le Royer, C. ; Tabone, C. ; Previtali, B. ; Jaud, M.-A. ; Garros, X. ; Vinet, M. ; Poiroux, T. ; Rafhay, Q. ; Mouis, M.
Author_Institution :
IMEP-LAHC, Grenoble-INP, Grenoble, France
fYear :
2011
Firstpage :
267
Lastpage :
270
Abstract :
In this work, an optimized method to extract GIDL parameters has been used to characterize junction quality in FDSOI devices. This paper gives a practical methodology to properly apply this method: first, it insists on the importance to discriminate the respective contributions of GIDL and gate tunneling in drain current. Then, an activation energy criterion is used to determine the bias conditions that are appropriate to correct application of this method. Experimental values of “tunneling” field and tunneling parameter are extracted, with better reliability than with previous methods. Reliable extractions of the GIDL parameters enable to characterize junction quality independently of junction abruptness and of the impact of traps in the bandgap. This method is successfully applied and results are in agreement with expected results.
Keywords :
MOSFET; elemental semiconductors; semiconductor device reliability; silicon; tunnelling; FDSOI device; GIDL parameter extraction; Si; activation energy criterion; bandgap trap; drain current; gate induced drain leakage parameter extraction; gate tunneling field; proper junction quality analysis; tunneling parameter extraction; Annealing; Electric fields; Hafnium compounds; Junctions; Logic gates; MOSFETs; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European
Conference_Location :
Helsinki
ISSN :
1930-8876
Print_ISBN :
978-1-4577-0707-0
Electronic_ISBN :
1930-8876
Type :
conf
DOI :
10.1109/ESSDERC.2011.6044183
Filename :
6044183
Link To Document :
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