Title :
Path Delay Fault Design For Test and Testability Analysis of Conditional Sum Adders
Author :
Decai, Yang ; Guangju, Chen ; Yongle, Xie
Author_Institution :
Univ. of Electron. Sci. & Technol. of China, Chengdu
Abstract :
Conditional sum adders (CSA) are kinds of high-speed adders and the existing delay faults have crucial influence on their performance. Detail path delay fault testability analysis is proposed and a design-for-test scheme with low overhead and low size of test set is presented which can guarantee single path propagating hazard-free fully robust path delay fault testability of CSA. This is the strictest requirement for path delay fault testing. Based on the scheme, a test set of minimal size is derived by exploiting its structural property and parallel testing.
Keywords :
adders; circuit testing; fault diagnosis; network synthesis; conditional sum adders; delay fault testability analysis; high-speed adders; path delay fault design; Adders; Automatic testing; Circuit faults; Design for testability; Electronic equipment testing; Hazards; Instruments; Performance analysis; Propagation delay; Robustness; design-for-test; path delay fault test;
Conference_Titel :
Electronic Measurement and Instruments, 2007. ICEMI '07. 8th International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-1-4244-1136-8
Electronic_ISBN :
978-1-4244-1136-8
DOI :
10.1109/ICEMI.2007.4350925
