DocumentCode
1729990
Title
Extended results for minimum-adder constant integer multipliers
Author
Gustafsson, Oscar ; Dempster, Andrew G. ; Wanhammar, Lars
Author_Institution
Dept. of Electr. Eng., Linkoping Univ., Sweden
Volume
1
fYear
2002
fDate
6/24/1905 12:00:00 AM
Abstract
By introducing simplifications to multiplier graphs we extend the previous work on minimum adder multipliers to five adders and show that this is enough to express all coefficients up to 19 bits. The average savings are more than 25% for 19 bits compared with CSD multipliers. The simplifications include addition reordering and vertex reduction to see that different graphs can generate the same coefficient sets. Thus, fewer graphs need to be evaluated. A classification of the graphs reduces the effort to search the coefficient space further.
Keywords
adders; directed graphs; fixed point arithmetic; multiplying circuits; 19 bit; addition reordering; coefficient sets; coefficient space; directed graphs; fixed-point number; minimum-adder constant integer multipliers; multiplier graphs; vertex reduction; Costs; Digital signal processing; Hardware; Network topology; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1009780
Filename
1009780
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