DocumentCode :
1730108
Title :
On dynamic delay and repeater insertion
Author :
Tenhunen, Hannu ; Pamunuwa, Dinesh
Author_Institution :
R. Inst. of Technol., Kista, Sweden
Volume :
1
fYear :
2002
fDate :
6/24/1905 12:00:00 AM
Abstract :
In deep sub-micron technologies, as the wires are placed ever closer and signal rise and fall times go into the sub-nano second region, increased crosstalk has implications on the data throughput and on signal integrity. Depending on the data correlation on the coupled lines, the delay can either decrease or increase. Here we show that in uniform coupled lines, the response for several important switching configurations has a dominant pole characteristic. This allows easy prediction for the average, worst-case and best-case delay of buffered lines. We show that the repeater numbering and sizing can be optimised to deal with crosstalk under different constraints to best match the application. Area and power issues are considered and all equations are checked against a dynamic circuit simulator (SPECTRE).
Keywords :
VLSI; circuit simulation; crosstalk; delays; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; poles and zeros; repeaters; SPECTRE; VLSI; average delay; best-case delay; buffered lines; crosstalk; data correlation; data throughput; deep sub-micron technologies; dominant pole characteristic; dynamic circuit simulator; dynamic delay; repeater insertion; signal fall times; signal integrity; signal rise times; switching configurations; uniform coupled lines; worst-case delay; Capacitance; Constraint optimization; Delay effects; Delay lines; Equations; Repeaters; Switches; Throughput; Very large scale integration; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1009786
Filename :
1009786
Link To Document :
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