• DocumentCode
    1730149
  • Title

    High-speed Viterbi decoder: an efficient scheduling method to exploit the pipelining

  • Author

    Bóo, M. ; Argüello, F. ; Bruguera, J.D. ; Zapata, E.L.

  • Author_Institution
    Dept. of Electron., Santiago de Compostela Univ., Spain
  • fYear
    1996
  • Firstpage
    165
  • Lastpage
    174
  • Abstract
    The main part of the Viterbi algorithm is a nonlinear feedback loop which presents a bottleneck for high-speed implementations. We present a novel scheduling scheme that allows increasing the available speed of the system. This is done through the utilization of look-ahead techniques to compute non-sequential data and, in this way, break the recursivity of the algorithm. This permits introducing pipelining. As a result, we obtain a speed growth comparable to previous parallel solutions, but with less hardware cost
  • Keywords
    Viterbi decoding; data compression; pipeline processing; high-speed Viterbi decoder; look-ahead techniques; nonlinear feedback loop; pipelining; scheduling method; scheduling scheme; Computer architecture; Costs; Decoding; Feedback loop; Hardware; Parallel processing; Pipeline processing; Processor scheduling; Shift registers; Viterbi algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Specific Systems, Architectures and Processors, 1996. ASAP 96. Proceedings of International Conference on
  • Conference_Location
    Chicago, IL
  • ISSN
    2160-0511
  • Print_ISBN
    0-8186-7542-X
  • Type

    conf

  • DOI
    10.1109/ASAP.1996.542811
  • Filename
    542811