DocumentCode :
1730278
Title :
Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application
Author :
Liu, Y.X. ; Mastukawa, T. ; Endo, K. ; Oruchi, S. ; Tsukada, J. ; Yamauchi, H. ; Ishikawa, Y. ; Sakamoto, K. ; Masahara, M. ; Kamei, T. ; Hayashida, T. ; Ogura, A.
Author_Institution :
Nanoelectron. Res. Inst., AIST, Ibaraki, Japan
fYear :
2011
Firstpage :
203
Lastpage :
206
Abstract :
The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (Tox). However, the σVt of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even Lg was down to 76 nm.
Keywords :
MOSFET; flash memories; 3D memory application; Si; poly-Si floating gate; scaled poly-Si channel FinFET; threshold voltage; tri-gate flash memories; variability analysis; FinFETs; Flash memory; Grain size; Logic gates; Silicon; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European
Conference_Location :
Helsinki
ISSN :
1930-8876
Print_ISBN :
978-1-4577-0707-0
Electronic_ISBN :
1930-8876
Type :
conf
DOI :
10.1109/ESSDERC.2011.6044199
Filename :
6044199
Link To Document :
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