Expert advisor for integrated virtual manufacturing and reliability for TSV/SiP based modules

The realization of vertical interconnected devices/chips using through silicon vias (TSVs) is one of the key emerging trends in 3D IC package. However, the new technology is in its R&D level and there are still many technical obstacles to overcome for it to be used for real products. For instance, some key technical challenges still exist in the TSV formation processes such as high aspect ratio via filling, wafer thinning and handling, etc. And the issue of reliability will become extraordinary crucial for TSV technology to be used in high volume production of electronic devices. The trial-and-error method is obviously not adaptable due to its time consuming and high cost due to the demanding pressure of time to market and time to profit. Therefore, there is an urgent need to develop innovative design methods for TSV/SiP based modules. In this paper, the efforts of the construction of an expert advisor for integrated virtual manufacturing and reliability design and evaluation for the TSV/SiP based modules are presented. Firstly, the material property database of TSV based package is built up through material property characterization by the submicron tester, dynamic mechanical analysis (DMA), thermal mechanical analysis (TMA) and nano-indentation. Secondly, novel modeling techniques for the copper electroplating, grinding and chemical mechanical planarization (CMP) and stacked bonding processes are developed for simulation of the whole manufacturing processes of TSV/SiP modules. Then the virtual prototyping method is used to validate and design the reliability of TSV/SiP modules such as stacked-dies packaging and hermetic MEMS packaging with the numerical simulation models of thermal cycling testing and electromigration testing. And finally the expert advisor for the TSV/SiP modules is integrated based on the results from the numerical modeling which are validated by the experiments.