Title :
On segmented channel routability
Author :
Hun, William N N ; Son, Xiaoyu ; Coppola, Alan ; Kennings, Andrew
Author_Institution :
Intel Archit. Group, Intel Corp., Hillsboro, OR, USA
fDate :
6/24/1905 12:00:00 AM
Abstract :
We address the problem of checking the routability of segmented channels using satisfiability. The segmented channel routing problem arises in the context of row-based field programmable gate arrays (FPGAs). Our approach transforms the routing task into a single large Boolean equation such that any assignment of input variables that satisfies the equation specifies a valid routing. It considers all nets simultaneously and the absence of a satisfying assignment implies that the channel is unroutable. Empirical results show that the method is time-efficient and applicable to large problem instances.
Keywords :
circuit layout CAD; computability; field programmable gate arrays; high level synthesis; integrated circuit layout; network routing; dogleg-free routability; doglegged routability; field programmable gate array; routability checking; row-based FPGAs; satisfiability; segmented channel routability; segmented channel routing problem; single large Boolean equation; Equations; Fabrics; Field programmable gate arrays; Input variables; Integer linear programming; Routing; Switches; Transforms;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1009804