Title :
Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits
Author :
Tanaka, Chika ; Saitoh, Masumi ; Ota, Kensuke ; Uchida, Ken ; Numata, Toshinori
Author_Institution :
Corp. R&D Center, Toshiba Corp., Yokohama, Japan
Abstract :
An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter is reduced 300 mV smaller than that of bulk-Tr.-based inverter due to the ideal sub-threshold slope. The performance benefits of NW-Tr.-based stacked circuit and SRAM cell are measured in terms of ultra-low voltage and ultra-low power operation.
Keywords :
CMOS integrated circuits; MOSFET; SPICE; SRAM chips; delays; elemental semiconductors; invertors; low-power electronics; nanowires; silicon; BSIM4 extraction; NW-transistor-based inverter; NW-transistor-based stacked circuit; SOI wafer; SPICE-based performance analysis; SRAM cell; Si; bulk-transistor-based CMOS circuit; bulk-transistor-based inverter; delay time; ideal subthreshold slope; power consumption; size 300 mm; ultralow voltage nanowire-transistor-based CMOS circuit; CMOS integrated circuits; Delay; Integrated circuit modeling; Inverters; Logic gates; Power demand; Semiconductor device modeling;
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0707-0
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2011.6044210
