Gated direct sequence spread spectrum clocking scheme for multimedia systems

Clock distribution is increasingly becoming a very important issue in the design of systems advancing by adding higher performance and speedier microprocessors. These enhancements typically require incorporating higher frequency clock oscillators because the clock speed is directly proportional to the speed of the microprocessor processing the information. A higher processor speed also presents challenging problems for developing systems with low electromagnetic interference (EMI) in order to comply with the rules and regulations specified by the United States Federal Communication Commission (FCC). In this paper, a gated direct sequence spread spectrum (GDSSS) clock distribution, where the original clock signal is being divided and spread over a wider frequency spectrum to reduce the radiated emissions, is proposed. A hardware including programmable logic devices and a system board with one GDSSS transmitter and three GDSSS receivers is designed to validate this new and scalable clock distribution concept. Reducing 10 dB radiated emissions greatly improved the video quality in multimedia systems without negatively affecting system timings.