Wavelet method for high-speed clock tree simulation

In this paper, we propose a fast wavelet collocation algorithm for high-speed clock tree simulation. Taking advantage of the specific structure of clock trees and the superior computational property of wavelets, the proposed algorithm presents the following merits. (1) It can perform both transient simulation and steady-state analysis with arbitrary input. (2) It employs nonlinear buffer model and nonuniform interconnect wire model. (3) It has a low computational complexity O(N) and can deal with considerably large circuits. (4) The proposed wavelet method works in time domain so that the simulation error in time domain can be well-controlled. Numerical experiment results demonstrate the promising features of the proposed algorithm in high-speed clock tree simulations.