Title :
Comparative study of circuit perspectives for multi-gate structures at sub-10nm node
Author :
Huguenin, J.-L. ; Lacord, J. ; Monfray, S. ; Coquand, R. ; Skotnicki, T. ; Ghibaudo, G. ; Boeuf, F.
Author_Institution :
ST Microelectron., Crolles, France
Abstract :
This work presents a comparative study between planar and vertical (FinFETs) multi-gate structures for 2017 ITRS specifications circuit perspectives. Propagation delays are simulated for inverter chain and NAND gate chain. Finally, the impact of the width is investigated on several design rules for FinFETs configurations.
Keywords :
MOSFET; logic gates; FinFET configuration; NAND gate chain; circuit perspectives; inverter chain; multigate structures; size 10 nm; Capacitance; FinFETs; Inverters; Logic gates; Propagation delay; Silicon; Substrates;
Conference_Titel :
Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0707-0
Electronic_ISBN :
1930-8876
DOI :
10.1109/ESSDERC.2011.6044223
